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Wilmington, North Carolina once had a thriving Black middle class and an elected interracial government. In 1898 white supremacists used violence to overthrow that government, kill Black residents and drive many others from the city.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
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The 130 nm process is a level of semiconductor process technology that was reached in the 2000–2001 timeframe by such leading semiconductor companies as Intel, Texas Instruments, IBM, and TSMC.
The origin of the 130 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
Some of the first CPUs manufactured with this process include Intel Tualatin family of Pentium III processors.
In 2020, American semiconductor company SkyWater Technology, in conjunction with Google and eFabless, released their 130 nm process design kit as open-source under the Apache License.[1] This was the first ever open-source PDK.[2]
| Preceded by 180 nm |
CMOS manufacturing processes | Succeeded by 90 nm |
 | This nanotechnology-related article is a stub. You can help Wikipedia by adding missing information. |
Source: Wikipedia. Article content is retrieved live through the MediaWiki API.
The 130 nm process is a level of semiconductor process technology that was reached in the 2000–2001 timeframe by such leading semiconductor companies as Intel, Texas Instruments, IBM, and TSMC. The origin of the 130 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS). Some of the first CPUs manufactured with this process include Intel Tualatin family of Pentium III processors. In 2020, American semiconductor company SkyWater Technology, in conjunction with Google and eFabless, released their 130 nm process design kit as open-source under the Apache License. This was the first ever open-source PDK.
The 90 nm process refers to the technology used in semiconductor manufacturing to create integrated circuits with a minimum feature size of 90 nanometers. It was an advancement over the previous 130 nm process. Eventually, it was succeeded by smaller process nodes, such as the 65 nm, 45 nm, and 32 nm processes. It was commercialized by the 2003–2005 timeframe, by semiconductor companies including Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology. The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS). The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter. The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition. Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.
The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.
The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. Toshiba produced commercial 32 GiB NAND flash memory chips with the 32 nm process in 2009. Intel and AMD produced commercial microchips using the 32 nm process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010. Since at least 1997, process nodes have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; none of the gate length, metal pitch, or gate pitch on a "32 nm" device are thirty-two nanometers. The 28 nm node is an intermediate half-node die shrink that appeared in production in 2010. It requires twice the number of design rules for ensuring reliability in manufacturing as 80 nm. According to a 2016 presentation by Sophie Wilson, 28 nm has the lowest cost per logic gate and has slowly risen since then. TSMC has offered 28 nm production using high-K metal gate process technology. GlobalFoundries offered "28SLPe" ("28 nm Super Low Power"). The successor to 32 nm was 22 nm, per the International Technology Roadmap for Semiconductors. Intel began mass production of 22 nm semiconductors in late 2011, and announced the release of its first commercial 22 nm devices in April 2012. TSMC bypassed 32 nm, jumping from 40 nm in 2008 to 28 nm in 2011.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Joe Louis.