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In 1968 Shirley Chisholm became the first Black woman elected to the United States Congress. In 1972 she launched a campaign for the Democratic presidential nomination, breaking another political barrier.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
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| Introduced | 2011 |
|---|---|
| Version | ARMv8-A, ARMv8-R, ARMv9-A |
| Encoding | AArch64/A64 and AArch32/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1] |
| Endianness | Bi for data only (little as default, instructions are little) |
| Extensions | |
| Registers | |
| General-purpose | 31 × 64-bit integer registers[1] |
| Floating-point | 32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography |
AArch64, also known as ARM64, is a 64-bit version of the ARM architecture family, a widely used set of computer processor designs. It was introduced in 2011 with the ARMv8 architecture and later became part of the ARMv9 series. AArch64 allows processors to handle more memory and perform faster calculations than earlier 32-bit versions. It is designed to work alongside the older 32-bit mode, known as AArch32, allowing compatibility with a wide range of software. Devices that use AArch64 include smartphones, tablets, personal computers, and servers. The AArch64 architecture has continued to evolve through updates that improve performance, security, and support for advanced computing tasks.[2]
In ARMv8-A, ARMv8-R, and ARMv9-A, an "Execution state" defines key characteristics of the processor’s environment. This includes the number of bits used in the primary processor registers, the supported instruction sets, and other aspects of the processor's execution environment. These versions of the ARM architecture support two Execution states: the 64-bit AArch64 state and the 32-bit AArch32 state.[3]
Extension: Data gathering hint (ARMv8.0-DGH).
AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A, and in all versions of ARMv9-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M.
The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28.
| Type | Bit | |||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | 0 | op0 | 0 | 0 | 0 | 0 | op1 | |||||||||||||||||||||||||
| SME | 1 | op0 | 0 | 0 | 0 | 0 | Varies | |||||||||||||||||||||||||
| Unallocated | 0 | 0 | 0 | 1 | ||||||||||||||||||||||||||||
| SVE | 0 | 0 | 1 | 0 | Varies | |||||||||||||||||||||||||||
| Unallocated | 0 | 0 | 1 | 1 | ||||||||||||||||||||||||||||
| Data Processing — Immediate PC-rel. | op | immlo | 1 | 0 | 0 | 0 | 0 | immhi | Rd | |||||||||||||||||||||||
| Data Processing — Immediate Others | sf | 1 | 0 | 0 | 01–11 | Rd | ||||||||||||||||||||||||||
| Branches + System Instructions | op0 | 1 | 0 | 1 | op1 | op2 | ||||||||||||||||||||||||||
| Load and Store Instructions | op0 | 1 | op1 | 0 | op2 | op3 | op4 | |||||||||||||||||||||||||
| Data Processing — Register | sf | op0 | op1 | 1 | 0 | 1 | op2 | op3 | ||||||||||||||||||||||||
| Data Processing — Floating Point and SIMD | op0 | 1 | 1 | 1 | op1 | op2 | op3 | |||||||||||||||||||||||||
Announced in October 2011,[5] ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit Execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit Execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit ARM) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provide user-space compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.[1] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[6] Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A.[7] The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it only runs in AArch32 mode.[8] ARMv8-A includes VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.[9]
An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.[10] For example, the ARM Cortex-A32 supports only AArch32,[11] the ARM Cortex-A34 supports only AArch64,[12] and the ARM Cortex-A72 supports both AArch64 and AArch32.[13] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.[10]
In December 2014, ARMv8.1-A,[14] an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.
Instruction set enhancements included the following:
Enhancements for the exception model and memory translation system included the following:
ARMv8.2-A was announced in January 2016.[17] Its enhancements fall into four categories:
The Scalable Vector Extension (SVE) is licensed as "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads.[18][19] The specification allows for ARM licensees to choose a hard-coded architectural register width between 128 and 2048 bits in multiples of 128. The extension is complementary to and does not replace the NEON extensions.
A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor; this computer[20] was the fastest supercomputer in the world for two years, from June 2020[21] to May 2022.[22] A more flexible version, 2x256 SVE, was implemented by the AWS Graviton3 ARM processor.
SVE is supported by GCC, with GCC 8 supporting automatic vectorization[19] and GCC 10 supporting C intrinsics. As of July 2020[update], LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.[23]
In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:[24]
ARMv8.3-A architecture is now supported by (at least) GCC 7.0.[29]
In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories:[30][31][32]
In September 2018, ARMv8.5-A was announced. Its enhancements fell into these categories:[34][35][36]
On 2 August 2019, Google announced Android will adopt Memory Tagging Extension (MTE).[38]
In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all features from ARMv8.5.[39][40][41] ARMv9-A also adds:
In September 2019, ARMv8.6-A was announced. Its enhancements fell into these categories:[34][47]
For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use.[49]
In September 2020, ARMv8.7-A was announced. Its enhancements fell into these categories:[34][50][51]
In September 2021, ARMv8.8-A and ARMv9.3-A were announced. Their enhancements fell into these categories:[34][54]
LLVM 15 supports ARMv8.8-A and ARMv9.3-A.[55]
In September 2022, ARMv8.9-A and ARMv9.4-A were announced, including:[56]
In October 2023, ARMv9.5-A was announced, including:[57]
In October 2024, ARMv9.6-A was announced, including:[59]
In October 2025, ARMv9.7-A was announced, including:[60]
In October 2026, ARMv9.8-A was announced, including:[62]
Optional AArch64 support was added to the Armv8-R profile, with the first Arm core implementing it being the Cortex-R82.[63] It adds the A64 instruction set, with some changes to the memory barrier instructions.[64]
pointer authentication extension is defined to be mandatory extension on ARMv8.3-A and is not optional
The ARMv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option. [..] The option -msign-return-address= is supported to enable return address protection using ARMv8.3-A Pointer Authentication Extensions.
Source: Wikipedia. Article content is retrieved live through the MediaWiki API.
AArch64, also known as ARM64, is a 64-bit version of the ARM architecture family, a widely used set of computer processor designs. It was introduced in 2011 with the ARMv8 architecture and later became part of the ARMv9 series. AArch64 allows processors to handle more memory and perform faster calculations than earlier 32-bit versions. It is designed to work alongside the older 32-bit mode, known as AArch32, allowing compatibility with a wide range of software. Devices that use AArch64 include smartphones, tablets, personal computers, and servers. The AArch64 architecture has continued to evolve through updates that improve performance, security, and support for advanced computing tasks.
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size. A computer that uses such a processor is a 64-bit computer. From the software perspective, 64-bit computing means the use of machine code with 64-bit virtual memory addresses. However, not all 64-bit instruction sets support full 64-bit virtual memory addresses; x86-64 and AArch64, for example, support only 48 bits of virtual address, with the remaining 16 bits of the virtual address required to be all zeros (000...) or all ones (111...), and several 64-bit instruction sets support fewer than 64 bits of physical memory address. The term 64-bit also describes a generation of computers in which 64-bit processors are the norm. 64 bits is a word size that defines certain classes of computer architecture, buses, memory, and CPUs and, by extension, the software that runs on them. 64-bit CPUs have been used in supercomputers since the 1970s (Cray-1, 1975) and in reduced instruction set computers (RISC) based workstations and servers since the early 1990s. In 2003, 64-bit CPUs were introduced to the mainstream PC market in the form of x86-64 processors and the PowerPC G5. A 64-bit register can hold any of 264 (over 18 quintillion or 1.8×1019) different values. The range of integer values that can be stored in 64 bits depends on the integer representation used. With the two most common representations, the range is 0 through 18,446,744,073,709,551,615 (equal to 264 − 1) for representation as an (unsigned) binary number, and −9,223,372,036,854,775,808 (−263) through 9,223,372,036,854,775,807 (263 − 1) for representation as two's complement. Hence, a processor with 64-bit memory addresses can directly access 264 bytes (16 exabytes or EB) of byte-addressable memory. With no further qualification, a 64-bit computer architecture generally has integer and addressing registers that are 64 bits wide, allowing direct support for 64-bit data types and addresses. However, a CPU might have external data buses or address buses with different sizes from the registers, even larger (the 32-bit Pentium had a 64-bit data bus, for instance).
CentOS (, from Community Enterprise Operating System; also known as CentOS Linux) is a discontinued Linux distribution that provided a free and open-source community-supported computing platform, functionally compatible with its upstream source, Red Hat Enterprise Linux (RHEL). In January 2014, CentOS announced the official joining with Red Hat while staying independent from RHEL, under a new CentOS governing board. The first CentOS release in May 2004, numbered as CentOS version 2, was forked from RHEL version 2.1AS. Since version 8, CentOS officially supports the x86-64, ARM64, and POWER8 architectures, and releases up to version 6 also supported the IA-32 architecture. As of December 2015, AltArch releases of CentOS 7 are available for the IA-32 architecture, Power ISA, and for the ARMv7hl and AArch64 variants of the ARM architecture. CentOS 8 was released on 24 September 2019. In December 2020, Red Hat unilaterally terminated CentOS development in favor of CentOS Stream 9, a distribution positioned upstream of RHEL. In March 2021, CloudLinux (makers of CloudLinux OS) released a RHEL derivative called AlmaLinux. Later in May 2021, one of the CentOS founders (Gregory Kurtzer) created the competing Rocky Linux project as a successor to the original mission of CentOS.
Libreboot (briefly known as GNU Libreboot) is a free and open-source software project based on coreboot, aimed at replacing some of the proprietary BIOS or UEFI firmware on supported x86-64 and AArch64 computers. Libreboot performs the basic machine setup such as CPU initialization or memory controller initialization necessary to load and run a 32-bit or 64-bit operating system, such as Linux or BSD. It was tested on FreeBSD, NetBSD, and OpenBSD.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →The Greenwood District.
