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Movements, leaders, victories and the continuing fight for equality.
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Meet the people whose lives, choices and achievements shaped the journey.
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In 1968 Shirley Chisholm became the first Black woman elected to the United States Congress. In 1972 she launched a campaign for the Democratic presidential nomination, breaking another political barrier.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
Windows Advanced Rasterization Platform (WARP)[1] is a software rasterizer and a component of the DirectX graphics runtime in Windows 7 and later. It is available for Windows Vista and Windows Server 2008 through the Platform Update for Windows Vista.
WARP can be used when no compatible hardware is available, in kernel mode applications or in a headless environment, or for remote rendering of Direct2D/DirectWrite for Remote Desktop Connection clients.
WARP is a fully featured Direct3D 10.1 renderer device with performance on par with low-end graphics cards, such as Intel GMA 3000,[2][needs update?] when running on multi-core CPUs.[3] To achieve this level of rendering performance, WARP employs advanced techniques such as just-in-time compilation to x86 machine code and support for advanced vector extensions such as SSE2 and SSE4.1. Since Windows 7 SP1, the WARP supports AVX.
WARP supports the Direct3D 11 runtime and is compatible with feature levels 10_1, 10_0, 9_3, 9_2, and 9_1. Under the Direct3D 11.1 runtime, WARP also supports feature levels 11_0 and 11_1.[4]
In Windows 8, WARP provides functionality for the Microsoft Basic Render Driver, which replaces the kernel-mode VGA driver. In Windows 8.1, WARP has been updated to support feature level 11_1 and tiled resources.[5]
In Windows 10, WARP was updated to support Direct3D 12 at feature level 12_1. Under Direct3D 12, WARP also replaces the Reference rasterizer.
In Windows 11, WARP was updated to support feature level 12_2 (DirectX 12 Ultimate) with variable rate shading, sampler feedback, mesh shaders, and DirectX Raytracing. Microsoft releases recent versions of d3d10warp.dll as a downloadable NuGet package,[6] which can be side-loaded by applications and can work with the redistributable Direct3D 12 runtime (Agility SDK).[7]
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Windows Advanced Rasterization Platform (WARP) is a software rasterizer and a component of the DirectX graphics runtime in Windows 7 and later. It is available for Windows Vista and Windows Server 2008 through the Platform Update for Windows Vista. WARP can be used when no compatible hardware is available, in kernel mode applications or in a headless environment, or for remote rendering of Direct2D/DirectWrite for Remote Desktop Connection clients. WARP is a fully featured Direct3D 10.1 renderer device with performance on par with low-end graphics cards, such as Intel GMA 3000, when running on multi-core CPUs. To achieve this level of rendering performance, WARP employs advanced techniques such as just-in-time compilation to x86 machine code and support for advanced vector extensions such as SSE2 and SSE4.1. Since Windows 7 SP1, the WARP supports AVX. WARP supports the Direct3D 11 runtime and is compatible with feature levels 10_1, 10_0, 9_3, 9_2, and 9_1. Under the Direct3D 11.1 runtime, WARP also supports feature levels 11_0 and 11_1. In Windows 8, WARP provides functionality for the Microsoft Basic Render Driver, which replaces the kernel-mode VGA driver. In Windows 8.1, WARP has been updated to support feature level 11_1 and tiled resources. In Windows 10, WARP was updated to support Direct3D 12 at feature level 12_1. Under Direct3D 12, WARP also replaces the Reference rasterizer. In Windows 11, WARP was updated to support feature level 12_2 (DirectX 12 Ultimate) with variable rate shading, sampler feedback, mesh shaders, and DirectX Raytracing. Microsoft releases recent versions of d3d10warp.dll as a downloadable NuGet package, which can be side-loaded by applications and can work with the redistributable Direct3D 12 runtime (Agility SDK).
Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge microarchitecture shipping in Q1 2011 and later by AMD with the Bulldozer microarchitecture shipping in Q4 2011. AVX provides new features, new instructions, and a new coding scheme. AVX2 (also known as Haswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with the Haswell microarchitecture, which shipped in 2013. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with Skylake server and HEDT processors in 2017.
A Touchstone file was originally a proprietary file format for the eponymous frequency-domain linear circuit simulator from EEsof, launched in 1984 and acquired by HP. The simulator has been called HP/EEsof, then its engine has been successively included in the jOmega and ADS software suites and it is now owned by Keysight. The Touchstone simulator has long since been superseded, but its file format lives on. A Touchstone file (also known as an SnP file after its set of file extensions) is an ASCII text file used for documenting the n-port network parameter data and noise data of linear active devices, passive filters, passive devices, or interconnect networks. An example of the format of the S-parameter section is given in the article about S-parameters. In addition to S-parameters, other representations such as Y-parameters and Z-parameters can be recorded. It later became a de facto industry-standard file format not only for circuit simulators but also for measurement equipment (e.g. vector network analyzers, or VNAs), then later still an EIA standard as part of the Input/output Buffer Information Specification (IBIS) project. On April 24, 2009, the IBIS Open Forum ratified version 2.0, superseding Version 1.1. Version 2.0 adds IBIS-style keywords such as [Reference], which permits per-port definition of the reference environment. More recently on January 26, 2024 the IBIS Open Forum released version 2.1 which clarified the filename extension, introduced more flexible definitions for reference values of the network, and made corrections to several examples. Several further enhancements to the file format that allow description of the non-linear behavior of the component have been developed under the P2D and S2D pair of formats, but these two have been superseded by the X-parameters functionality.
AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and first implemented in the 2016 Intel Xeon Phi x200 (Knights Landing), and then later in a number of AMD and other Intel CPUs (see list below). AVX-512 consists of multiple extensions that may be implemented independently. This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all AVX-512 implementations. Besides widening most 256-bit instructions, the extensions introduce various new operations, such as new data conversions, scatter operations, and permutations. The number of AVX registers is increased from 16 to 32, and eight new "mask registers" are added, which allow for variable selection and blending of the results of instructions. In CPUs with the vector length (VL) extension—included in most AVX-512-capable processors (see § CPUs with AVX-512)—these instructions may also be used on the 128-bit and 256-bit vector sizes. AVX-512 is not the first 512-bit SIMD instruction set that Intel has introduced in processors: the earlier 512-bit SIMD instructions used in the first generation Xeon Phi coprocessors, derived from Intel's Larrabee project, are similar but not binary compatible and only partially source compatible. The successor to AVX-512 is AVX10, announced in July 2023. AVX10 simplifies detection of supported instructions by introducing a version of the instruction set, where each subsequent version includes all instructions from the previous one. In the initial revisions of the AVX10 specification, the support for 512-bit vectors was made optional, which would allow Intel to support it in their E-cores. In later revisions, Intel made 512-bit vectors mandatory, with the intention to support 512-bit vectors both in P- and E-cores. The initial version 1 of AVX10 does not add new instructions compared to AVX-512, and for processors supporting 512-bit vectors it is equivalent to AVX-512 (in the set supported by Intel Sapphire Rapids processors). Later AVX10 versions will introduce new features.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Madam C.J. Walker
