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Mansa Musa was the ruler of the Mali Empire in West Africa. Details recorded here should be sourced; unknown information is left blank.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.[1]
Originally, CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.
The concept was first proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable in 1993. The first concept demonstration however came from Mitsubishi Electric.[2]
The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer-level package (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as Advanced Semiconductor Engineering (ASE).[3][4]
Chip scale packages can be classified into the following groups:
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Source: Wikipedia. Article content is retrieved live through the MediaWiki API.
A chip scale package or chip-scale package (CSP) is a type of integrated circuit package. Originally, CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm. The concept was first proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable in 1993. The first concept demonstration however came from Mitsubishi Electric. The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer-level package (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as Advanced Semiconductor Engineering (ASE).
Transistor arrays consist of two or more transistors on a common substrate. Unlike more highly integrated circuits, the transistors can be used individually like discrete transistors. That is, the transistors in the array are not connected to each other to implement a specific function. Transistor arrays can consist of bipolar junction transistors or field-effect transistors. There are three main motivations for combining several transistors on one chip and in one package: to ensure closely matching parameters between the transistors (which is almost guaranteed when the transistors on one chip are manufactured simultaneously and subject to identical manufacturing process variations) to ensure a closely matching thermal drift of parameters between the transistors (which is achieved by having the transistors on a common substrate, and in extremely close proximity) to save circuit board space and to reduce board production cost (only one component needs to be populated instead of several) The matching parameters and thermal drift are crucial for various analogue circuits such as differential amplifiers, current mirrors, and log amplifiers. The reduction in circuit board area is particularly significant for digital circuits where several switching transistors are combined in one package. Often the transistors here are Darlington pairs with a common emitter and flyback diodes, e.g. ULN2003A. While this stretches the above definition of a transistor array somewhat, the term is still commonly applied. A peculiarity of transistor arrays is that the substrate is often available as a separate pin (labelled substrate, bulk, or ground). Care is required when connecting the substrate in order to maintain isolation between the transistors in the array as p–n junction isolation is usually used. For instance, for an array of NPN transistors, the substrate must be connected to the most negative voltage in the circuit.
Embedded wafer level ball grid array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound. eWLB is a further development of the classical wafer level ball grid array technology (WLB or WLP: wafer level package). The main driving force behind the eWLB technology was to allow fanout and more space for interconnect routing. All process steps for the generation of the package are performed on the wafer. This allows, in comparison to classical packaging technologies (e. g. ball grid array), the generation of very small and flat packages with excellent electrical and thermal performance at lowest cost. It is common for all WLB technologies, which are built on a silicon wafer, that the interconnects (typically solder balls) fit on the chip (so called fan-in design). Therefore only chips with a restricted number of interconnects can be packaged. The eWLB technology allows the realization of chips with a high number of interconnects. The package is not created on a silicon wafer as for the classical wafer level package, but on an artificial wafer. Therefore a front-end-processed wafer is diced and the singulated chips are placed on a carrier. The distance between the chips can be chosen freely, but it is typically larger than on the silicon wafer. The gaps and the edges around the chips are now filled with a casting compound to form a wafer. After curing an artificial wafer containing a mold frame around the dies for carrying additional interconnect elements is created. After the build of the artificial wafer (the so-called reconstitution) the electrical connections from the chip pads to the interconnects are made in thin-film technology, as for any other classical wafer level package. With this technology any number of additional interconnects can be realized on the package in an arbitrary distance (fan-out design). Therefore, this wafer level packaging technology can also be used for space sensitive applications, where the chip area wouldn’t be sufficient to place the required number of interconnects at a suitable distance. The eWLB technology was developed by Infineon, STMicroelectronics and STATS ChipPAC Ltd. First components were brought into market mid of 2009 (mobile phone).
Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment. As of 2009, there is no single industry-standard method of wafer-level packaging. A major application area of WLPs is their use in smartphones due to the size constraints. For example, the Apple iPhone 5 has at least eleven different WLPs, the Samsung Galaxy S3 has six WLPs and the HTC One X has seven. Functions provided WLPs in smartphones include sensors, power management, and wireless. The iPhone 7 was rumored to use fan-out wafer-level packaging technology in order to achieve a thinner and lighter model. Wafer-level chip scale packaging (WL-CSP) is the smallest package currently available on the market and is produced by OSAT (Outsourced Semiconductor Assembly and Test) companies, such as Advanced Semiconductor Engineering (ASE). A WL-CSP or WLCSP package is just a bare die with a redistribution layer (RDL, interposer or I/O pitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like a ball grid array (BGA) package. The RDL is often made out of a polyamide or polybenzoxazole with copper plated on its surface. There are two kinds of wafer level packaging: fan-in and fan-out. Fan-in WLCSP packages have an interposer that is the same size as that of the die, where as fan-out WLCSP packages have an interposer that is larger than the die, similar to conventional BGA packages, the difference being that the interposer is built directly atop the die, instead of the die being attached to it and reflowed using the flip chip method. This is also true in fan-in WLSCP packages. In both cases, the die with its interposer may be covered in encapsulating material such as epoxy. Fan-out packages are used in cases where fan-in packages are not able to provide enough connections at a specified cost. In February 2015, it was discovered that a WL-CSP chip in the Raspberry Pi 2 had issues with xenon flashes (or any other bright flashes of longwave light), inducing the photoelectric effect within the chip.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Brown v. Board of Education in 1954.
