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Movements, leaders, victories and the continuing fight for equality.
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Meet the people whose lives, choices and achievements shaped the journey.
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Katherine Johnson’s mathematical calculations helped guide some of America’s most important early space missions while she confronted the racial and gender barriers faced by Black women in twentieth-century America.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
The AMD Bulldozer Family 15h is a microprocessor microarchitecture for the FX and Opteron line of processors, developed by AMD for the desktop and server markets. Bulldozer is the codename for this family of microarchitectures. It was released on October 12, 2011, as the successor to the K10 microarchitecture. Bulldozer is designed from scratch, not a development of earlier processors. The core is specifically aimed at computing products with TDPs of 10 to 125 watts. AMD claims dramatic performance-per-watt efficiency improvements in high-performance computing (HPC) applications with Bulldozer cores. The Bulldozer cores support most of the instruction sets implemented by Intel processors (Sandy Bridge) available at its introduction (including SSSE3, SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD; ABM, XOP, FMA4 and F16C. Only Bulldozer GEN4 (Excavator) supports AVX2 instruction sets.
The SSE5 (short for Streaming SIMD Extensions version 5) was a SIMD instruction set extension proposed by AMD on August 30, 2007 as a supplement to the 128-bit SSE core instructions in the AMD64 architecture. AMD chose not to implement SSE5 as originally proposed. In May 2009, AMD replaced SSE5 with three smaller instruction set extensions named as XOP, FMA4, and F16C, which retain the proposed functionality of SSE5, but encode the instructions differently for better compatibility with Intel's proposed AVX instruction set. The three SSE5-derived instruction sets were introduced in the Bulldozer processor core, released in October 2011 on a 32 nm process.
The FMA instruction set is an extension to the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations on 128-bit and 256-bit operands. These operations were extended to 512-bit operands by the AVX-512 extension introduced by Intel and later supported by AMD. There are two incompatible variants of the FMA instruction set. They have the same operations but differ in the number of operands: FMA4 is the four-operand variant (three source operands and a destination register). AMD added FMA4 with the Bulldozer (2011) architecture. Zen 1 (2017) processors still execute FMA4 instructions but do not report them as supported through CPUID, and Zen 2 (2019) removed them. Intel originally specified FMA4 in 2008, but changed its design to three operands later that year. FMA3 is the three-operand variant (three source operands, one of which is also the destination). AMD added FMA3 with the Piledriver (2012) architecture, for compatibility with Intel's planned Haswell processors. Intel added FMA3, alongside AVX2, with Haswell (2013) processors. Earlier processors, including AMD's Bulldozer and Intel's Sandy Bridge and Ivy Bridge, do not support it. AVX-512 adds 512-bit forms of the FMA3 instructions.
In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in its Pentium III series of central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!. SSE contains 70 new instructions (65 unique mnemonics using 70 encodings), most of which work on single precision floating-point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing. Intel's first IA-32 SIMD effort was the MMX instruction set. MMX had two main problems: it re-used existing x87 floating-point registers making the CPUs unable to work on both floating-point and SIMD data at the same time, and it only worked on integers. SSE floating-point instructions operate on a new independent register set, the XMM registers, and adds a few integer instructions that work on MMX registers. SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3 and SSE4. Because it supports floating-point math, it had wider applications than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations. SSE was originally called Katmai New Instructions (KNI), Katmai being the code name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from its earlier product line, particularly its flagship Pentium II. It was later renamed Internet Streaming SIMD Extensions (ISSE), then SSE. AMD added a subset of SSE, 19 of them, called new MMX instructions, and known as several variants and combinations of SSE and MMX, or otherwise as Integer SSE (ISSE, not to be confused with Internet Streaming SIMD Extensions, an early name for SSE) shortly after with the release of the original Athlon in August 1999 (see 3DNow! extensions). AMD eventually added full support for SSE instructions (sometimes referred to as 3DNow! Professional) starting with its Athlon XP (Corvette and Palomino cores) and Duron (Morgan core) processors.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Joe Louis.