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Computing with memory (or in-memory computing, IMC) is a paradigm that performs computations directly within memory arrays (RAM, RRAM, PCM) rather than transferring data to a separate CPU, significantly reducing energy consumption and latency. It addresses the von Neumann bottleneck by enabling data-parallel operations, such as for neural networks and big data analytics, at speeds up to thousands of times faster than traditional storage methods. These paradigms can follow either a purely spatial computing model or a temporal computing model. The latter approach aims at reducing overheads in FPGAs. Computing with memory differs from computing in memory or processor-in-memory concepts.

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These paradigms can follow either a purely spatial computing model, as in field-programmable gate array (FPGA), or a temporal computing model, where a function is evaluated across multiple clock cycles. The latter approach aims at reducing the overhead of programmable interconnect in FPGA by folding interconnect resources inside a computing element. It uses dense two-dimensional memory arrays to store large multiple-input multiple-output LUTs. Computing with memory differs from computing in memory or processor-in-memory (PIM) concepts, widely investigated in the context of integrating a processor and memory on the same chip to reduce memory latency and increase bandwidth. These architectures seek to reduce the distance the data travels between the processor and the memory. The Berkeley IRAM project is one notable contribution in the area of PIM architectures.

Computing with memory platforms are typically used to provide the benefit of hardware reconfigurability. Reconfigurable computing platforms offer advantages in terms of reduced design cost, early time-to-market, rapid prototyping and easily customizable hardware systems. FPGAs present a popular reconfigurable computing platform for implementing digital circuits. They follow a purely spatial computing model. Since their inception in 1985, the basic structure of the FPGAs has continued to consist of two-dimensional array of configurable logic blocks (CLBs) and a programmable interconnect matrix.^[1] FPGA performance and power dissipation is largely dominated by the elaborate programmable interconnect (PI) architecture.^[2][3] An effective way of reducing the impact of the PI architecture in FPGA is to place small LUTs in close proximity (referred as clusters) and to allow intra-cluster communication using local interconnects. Due to the benefits of a clustered FPGA architecture, major FPGA vendors have incorporated it in their commercial products.^[4][5] Investigations have also been made to reduce the overhead due to PI in fine-grained FPGAs by mapping larger multi-input multi-output LUTs to embedded memory blocks. Although it follows a similar spatial computing model, part of the logic functions are implemented using embedded memory blocks while the remaining part is realized using smaller LUTs.^[6] Such a heterogeneous mapping can improve the area and performance by reducing the contribution of programmable interconnects.

Contrary to the purely spatial computing model of FPGA, a reconfigurable computing platform that employs a temporal computing model (or a combination of both temporal and spatial) has also been investigated^[7][8] in the context of improving performance and energy over conventional FPGA. These platforms, referred as "memory-based computing" (MBC), use dense two-dimensional memory array to store the LUTs. Such frameworks rely on breaking a complex function (f) into small sub-functions; representing the sub-functions as multi-input, multi-output LUTs in the memory array; and evaluating the function f over multiple cycles. MBC can leverage on the high density, low power and high performance advantages of nanoscale memory.^[8]

Each computing element incorporates a two-dimensional memory array for storing LUTs, a small controller for sequencing evaluation of sub-functions and a set of temporary registers to hold the intermediate outputs from individual partitions. A fast, local routing framework inside each computing block generates the address for LUT access. Multiple such computing elements can be spatially connected using FPGA-like programmable interconnect architecture to enable mapping of large functions. The local time-multiplexed execution inside the computing elements can drastically reduce the requirement of programmable interconnects leading to large improvement in energy-delay product and better scalability of performance across technology generations. The memory array inside each computing element can be realized by content-addressable memory (CAM) to drastically reduce the memory requirement for certain applications.^[7]

• Computational RAM
• Field-programmable gate array (FPGA)
• Memoization
• Reconfigurable computing