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A logic analyzer is an electronic instrument that captures and displays multiple logic signals from a digital system or digital circuit. A logic analyzer may convert the capture into timing diagrams, protocol decodes, state machine traces, opcodes, or may correlate opcodes with source-level software. Logic analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system.^[1]

Presently, there are three distinct categories of logic analyzers available on the market:

• Modular LAs, which consist of both a chassis or mainframe and logic analyzer modules.^[2] The mainframe/chassis contains the display, controls, control computer, and multiple slots into which the actual data-capturing hardware is installed. The modules each have a specific number of channels, and multiple modules may be combined to obtain a very high channel count. While modular logic analyzers are typically more expensive, the ability to combine multiple modules to obtain a high channel count and the generally higher performance of modular logic analyzers often justifies the price. For the very high end modular logic analyzers, the user often must provide their own host PC or purchase an embedded controller compatible with the system.^[3]

• Portable LAs,^[4] sometimes referred to as standalone LAs. Portable logic analyzers integrate everything into a single package, with options installed at the factory. While portable logic analyzers generally have lower performance than their modular counterparts, they are often used for general purpose debugging by cost conscious users.
• PC-based LAs. The hardware connects to a computer through a USB or Ethernet connection and relays the captured signals to the software on the computer. These devices are typically much smaller and less expensive because they make use of a PC's existing keyboard, display and CPU.

A logic analyzer can be triggered on a complicated sequence of digital events, then capture a large amount of digital data from the system under test (SUT).

When logic analyzers first came into use, it was common to attach several hundred "clips" to a digital system. Later, specialized connectors came into use. The evolution of logic analyzer probes has led to a common footprint that multiple vendors support, which provides added freedom to end users. Introduced in April, 2002, connectorless technology (identified by several vendor-specific trade names: Compression Probing; Soft Touch; D-Max) has become popular. These probes provide a durable, reliable mechanical and electrical connection between the probe and the circuit board with less than 0.5 to 0.7 pF loading per signal.

Once the probes are connected, the user programs the analyzer with the names of each signal, and can group several signals together for easier manipulation. Next, a capture mode is chosen, either "timing" mode, where the input signals are sampled at regular intervals based on an internal or external clock source, or "state" mode, where one or more of the signals are defined as "clocks", and data are taken on the rising or falling edges of these clocks, optionally using other signals to qualify these clocks.

After the mode is chosen, a trigger condition must be set. A trigger condition can range from simple (such as triggering on a rising or falling edge of a single signal) to the very complex (such as configuring the analyzer to decode the higher levels of the TCP/IP stack and triggering on a certain HTTP packet).

At this point, the user sets the analyzer to "run" mode, either triggering once, or repeatedly triggering.

Once the data are captured, they can be displayed several ways, from the simple (showing waveforms or state listings) to the complex (showing decoded Ethernet protocol traffic). Some analyzers can also operate in a "compare" mode, where they compare each captured data set to a previously recorded data set, and halt capture or visually notify the operator when this data set is either matched or not. This is useful for long-term empirical testing. Recent analyzers can even be set to email a copy of the test data to the engineer on a successful trigger.

Many digital designs, including those of ICs, are simulated to detect defects before the unit is constructed. The simulation usually provides logic analysis displays. Often, complex discrete logic is verified by simulating inputs and testing outputs using boundary scan. Logic analyzers can uncover hardware defects that are not found in simulation. These problems are typically too difficult to model in simulation, or too time-consuming to simulate and often cross multiple clock domains.

Field-programmable gate arrays have become a common measurement point for logic analyzers and are also used to debug the logic circuit.

Logic Analyzers are also very useful when it comes to analyze serial protocols, like I2C, SPI or UART, as they allow to capture long logic sequences showing one or several communication frames. Usually, the Logic Analyzer software will also interpret the protocol layer, making the debugging of firmware a less tedious task.

As digital computing and integrated circuits emerged in the 1960s,^[5] new and difficult problems began to arise, problems that oscilloscopes had trouble handling. For the first time in computing history, it became essential to simultaneously view large numbers of signals. Early solutions attempted to combine hardware from multiple oscilloscopes into one package, but screen clutter, a lack of definite data interpretation, as well as probing constraints made this solution only marginally usable.

The HP 5000A Logic Analyzer, introduced in the October 1973 issue of the Hewlett-Packard Journal, was probably the first commercially available instrument to be called a "Logic Analyzer". However, the HP 5000A was limited to two channels and presented information by means of two rows of 32 LEDs. The first truly parallel instrument was the twelve channel HP 1601L, it was a plug-in for the HP 180 series oscilloscope mainframes and used the oscilloscope screen to present 16 rows of 12 bit words as 1s and 0s. It was introduced in the January 1974 Hewlett-Packard Journal.^[6]

Mixed-signal oscilloscopes combine the functionality of a digital storage oscilloscope with a logic analyzer. The several benefits of these include the ability to view analog and digital signals together in time, and to trigger on either digital or analog signals and capture on the other. A few limitations of mixed signal oscilloscopes are that they do not capture state-mode data, they have a limited channel count, and do not provide the analytical depth and insight of a logic analyzer.

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• Feeling Comfortable with Logic Analyzers - Keysight

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