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In 1968 Shirley Chisholm became the first Black woman elected to the United States Congress. In 1972 she launched a campaign for the Democratic presidential nomination, breaking another political barrier.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
SiCortex was a supercomputer manufacturer founded in 2003 and headquartered in Clock Tower Place, Maynard, Massachusetts. On 27 May 2009, HPCwire reported that the company had shut down its operations, laid off most of its staff, and is seeking a buyer for its assets.[1] The Register reported that Gerbsman Partners was hired to sell SiCortex's intellectual properties.[2] While SiCortex had some sales, selling at least 75 prototype supercomputers to several large customers, the company had never produced an operating profit and ran out of venture capital. New funding could not be found.
The company built and marketed a family of clusters of between 12 and 972 compute nodes, connected in a Kautz graph. The clusters are the SC5832, SC648 and SC072. It was reported that the company has been working on the next generation of clusters since March 2009, but development ceased when operations were closed.
The SC5832 is a high-end model housed in a cabinet. It has 972 nodes, 5,832 cores and 972 to 7,776 GB of memory. It uses a diameter-6 Kautz graph for 2,916 links. The SC648 is a mid-range model housed in a standard 19-inch rack. Each rack may contain two systems. It has 108 nodes, 648 cores and 108 to 864 GB of memory. It uses a diameter-4 Kautz graph for 324 links. The SC072 is a desktop model for developing software.
Each node is system-on-chip (SoC), codenamed ICE9,[3] consisting of six cores that implement the MIPS64 instruction set architecture (ISA). Each core has a 32 KB instruction cache and a 32 KB data cache. The six cores have their own 256 KB L2 cache, which can be accessed by other cores. The MIPS cores execute instructions in-order and have a six-stage pipeline. They can issue and execute two instructions per cycle for peak double-precision (64-bit) performance of 1 GFLOPS at 500 MHz. This was later increased to 1.4 GFLOPS when the clock frequency of the SoC was increased to 700 MHz when the SoC was fabricated in a 90 nm process. The SoC contains two DDR2 memory controllers, each controlling a single DIMM. Each node can have 1 to 8 GB of memory. The SoC also implements a 8x PCI Express controller. The cluster interconnect is implemented by a DMA engine fabric switch. Each cluster interconnect provides a maximum bandwidth of 2 GB/s.
Message passing, via MPI, is the presumptive programming model. SiCortex systems run a customized Linux distribution derived from Gentoo Linux.
| Model # | Nodes | Codename | Notes |
|---|---|---|---|
| SC5832 | 972 | Blizzard | 36 blades |
| SC1458 | 243 | Hail | 9 blades |
| SC648 | 108 | Snow | 4 blades |
| SC162 | 27 | Sleet | a single blade |
| SC072 "Catapult" | 12 | Flurry | Standard Workstation for Application Development |
| SC24 | 4 | Frost | Diagnostic board |
Source: Wikipedia. Article content is retrieved live through the MediaWiki API.
SiCortex was a supercomputer manufacturer founded in 2003 and headquartered in Clock Tower Place, Maynard, Massachusetts. On 27 May 2009, HPCwire reported that the company had shut down its operations, laid off most of its staff, and is seeking a buyer for its assets. The Register reported that Gerbsman Partners was hired to sell SiCortex's intellectual properties. While SiCortex had some sales, selling at least 75 prototype supercomputers to several large customers, the company had never produced an operating profit and ran out of venture capital. New funding could not be found. The company built and marketed a family of clusters of between 12 and 972 compute nodes, connected in a Kautz graph. The clusters are the SC5832, SC648 and SC072. It was reported that the company has been working on the next generation of clusters since March 2009, but development ceased when operations were closed. The SC5832 is a high-end model housed in a cabinet. It has 972 nodes, 5,832 cores and 972 to 7,776 GB of memory. It uses a diameter-6 Kautz graph for 2,916 links. The SC648 is a mid-range model housed in a standard 19-inch rack. Each rack may contain two systems. It has 108 nodes, 648 cores and 108 to 864 GB of memory. It uses a diameter-4 Kautz graph for 324 links. The SC072 is a desktop model for developing software. Each node is system-on-chip (SoC), codenamed ICE9, consisting of six cores that implement the MIPS64 instruction set architecture (ISA). Each core has a 32 KB instruction cache and a 32 KB data cache. The six cores have their own 256 KB L2 cache, which can be accessed by other cores. The MIPS cores execute instructions in-order and have a six-stage pipeline. They can issue and execute two instructions per cycle for peak double-precision (64-bit) performance of 1 GFLOPS at 500 MHz. This was later increased to 1.4 GFLOPS when the clock frequency of the SoC was increased to 700 MHz when the SoC was fabricated in a 90 nm process. The SoC contains two DDR2 memory controllers, each controlling a single DIMM. Each node can have 1 to 8 GB of memory. The SoC also implements a 8x PCI Express controller. The cluster interconnect is implemented by a DMA engine fabric switch. Each cluster interconnect provides a maximum bandwidth of 2 GB/s. Message passing, via MPI, is the presumptive programming model. SiCortex systems run a customized Linux distribution derived from Gentoo Linux.
QLogic Corporation was an American manufacturer of networking server and storage networking connectivity and application acceleration products, based in Aliso Viejo, California through 2016. QLogic's products include Fibre Channel adapters, converged network adapters for Fibre Channel over Ethernet (FCoE), Ethernet network interface controllers, iSCSI adapters, and application-specific integrated circuits (ASICs). It was a public company from 1992 to 2016.
A multi-core processor (MCP) is a microprocessor on a single integrated circuit (IC) with two or more separate central processing units (CPUs), called cores to emphasize their multiplicity (for example, dual-core or quad-core). Each core reads and executes program instructions, specifically ordinary CPU instructions (such as add, move data, and branch). However, the MCP can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single IC die, known as a chip multiprocessor (CMP), or onto multiple dies in a single chip package. As of 2024, the microprocessors used in almost all new personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies used to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have cores that are not identical (e.g. big.LITTLE have heterogeneous cores that share the same instruction set, while AMD Accelerated Processing Units have cores that do not share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading. Multi-core processors are widely used across many application domains, including general-purpose, embedded, network, digital signal processing (DSP), and graphics (GPU). Core count goes up to even dozens, and for specialized chips over 10,000, and in supercomputers (i.e. clusters of chips) the count can go over 10 million (and in one case up to 20 million processing elements total in addition to host processors). The improvement in performance gained by the use of a multi-core processor depends very much on the software algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores; this effect is described by Amdahl's law. In the best case, so-called embarrassingly parallel problems may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each core's cache(s), avoiding use of much slower main-system memory. Most applications, however, are not accelerated as much unless programmers invest effort in refactoring. The parallelization of software is a significant ongoing topic of research. Cointegration of multiprocessor applications provides flexibility in network architecture design. Adaptability within parallel models is an additional feature of systems utilizing these protocols. In the consumer market, dual-core processors (that is, microprocessors with two units) started becoming commonplace on personal computers in the late 2000s. In the early 2010s, quad-core processors were also being adopted in that era for higher-end systems before becoming standard by the mid 2010s. In the late 2010s, hexa-core (six cores) started entering the mainstream and since the early 2020s has overtaken quad-core in many spaces.
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to 3D computer graphics; MDMX (MaDMaX), a more extensive integer SIMD instruction set using 64-bit floating-point registers; MIPS16e, which adds compression to the instruction stream to reduce the memory programs require; and MIPS MT, which adds multithreading capability. Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to RISC-V.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Shirley Chisholm, elected in 1968.