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Katherine Johnson’s mathematical calculations helped guide some of America’s most important early space missions while she confronted the racial and gender barriers faced by Black women in twentieth-century America.
MORE →Reflects the personal views, recollections, and perspective of the author, Mike Davis.
This is a personal recollection on the Move fire on May 13, 1985
Supervisor Mode Access Prevention (SMAP) is a feature of some CPU implementations such as the Intel Broadwell microarchitecture that allows supervisor mode programs to optionally set user-space memory mappings so that access to those mappings from supervisor mode will cause a trap. This makes it harder for malicious programs to "trick" the kernel into using instructions or data from a user-space program.[1][2]
Supervisor Mode Access Prevention is designed to complement Supervisor Mode Execution Prevention (SMEP), which was introduced earlier. SMEP can be used to prevent supervisor mode from unintentionally executing user-space code. SMAP extends this protection to reads and writes.[2]
Without Supervisor Mode Access Prevention, supervisor code usually has full read and write access to user-space memory mappings (or has the ability to obtain full access). This has led to the development of several security exploits, including privilege escalation exploits, which operate by causing the kernel to access user-space memory when it did not intend to.[3] Operating systems can block these exploits by using SMAP to force unintended user-space memory accesses to trigger page faults. Additionally, SMAP can expose flawed kernel code which does not follow the intended procedures for accessing user-space memory.[1]
However, the use of SMAP in an operating system may lead to a larger kernel size and slower user-space memory accesses from supervisor code, because SMAP must be temporarily disabled any time supervisor code intends to access user-space memory.[4]
Processors indicate support for Supervisor Mode Access Prevention through the Extended Features CPUID leaf.
SMAP is enabled when memory paging is active and the SMAP bit in the CR4 control register is set. SMAP can be temporarily disabled for explicit memory accesses by setting the EFLAGS.AC (Alignment Check) flag. The stac (Set AC Flag) and clac (Clear AC Flag) instructions can be used to easily set or clear the flag.[5]
When the SMAP bit in CR4 is set, explicit memory reads and writes to user-mode pages performed by code running with a privilege level less than 3 will always result in a page fault if the EFLAGS.AC flag is not set. Implicit reads and writes (such as those made to descriptor tables) to user-mode pages will always trigger a page fault if SMAP is enabled, regardless of the value of EFLAGS.AC.[5]
Linux kernel support for Supervisor Mode Access Prevention was implemented by H. Peter Anvin.[1] It was merged into the mainline Linux 3.7 kernel (released December 2012) and it is enabled by default for processors which support the feature.[4]
FreeBSD has supported Supervisor Mode Execution Prevention since 2012[6] and Supervisor Mode Access Prevention since 2018.[7]
OpenBSD has supported Supervisor Mode Access Prevention and the related Supervisor Mode Execution Prevention since 2012,[8] with OpenBSD 5.3 being the first release with support for the feature enabled.[9]
NetBSD support for Supervisor Mode Execution Prevention (SMEP) was implemented by Maxime Villard in December 2015.[10] Support for Supervisor Mode Access Prevention (SMAP) was also implemented by Maxime Villard, in August 2017.[11] NetBSD 8.0 was the first release with both features supported and enabled.[12]
Haiku support for Supervisor Mode Execution Prevention (SMEP) was implemented by Jérôme Duval in January 2018.[13]
macOS has support for SMAP at least since macOS 10.13 released 2017.[14]
Source: Wikipedia. Article content is retrieved live through the MediaWiki API.
Supervisor Mode Access Prevention (SMAP) is a feature of some CPU implementations such as the Intel Broadwell microarchitecture that allows supervisor mode programs to optionally set user-space memory mappings so that access to those mappings from supervisor mode will cause a trap. This makes it harder for malicious programs to "trick" the kernel into using instructions or data from a user-space program.
The Zilog Z280 is a 16-bit microprocessor designed by Zilog as an enhancement of the Zilog Z80 architecture and integrating improvements from the abandoned Zilog Z800 project. First introduced in July 1987, the Z280 is considered to be a commercial failure. The Z280 was fabricated in CMOS, added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes (four total possible address spaces). Its crystal or external clock signal is divided by half to drive the CPU. The CPU clock can be further divided by 1, 2, or 4 times to drive the bus (e.g. 12 MHz CPU divided by 4 will drive the bus at 3 MHz). Unlike the Z80 the Z280 multiplexes the lowest byte of its address onto the data bus; the rest of the address lines are not multiplexed. If running in Z-BUS mode, the data bus is expanded to 16 bits, multiplexed with the lower 16 bits of address. Although the z280 universally handles 16-bit math, moves, and even has a 16-bit bus option, it only supports 8-bit operations for logic functions such as AND, OR, and XOR. More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others. The Z280 had many advanced features for its time: On-chip instruction and/or data cache, or on-chip RAM Instruction pipelining High performance 16-bit Z-BUS interface or 8-bit Z80-compatible bus interface Built-in MMU with memory protection Ability to determine which register set is in context with instructions JAF and JAR Three on-chip 16-bit counter/timers Four on-chip DMA channels On-chip full duplex UART User I/O trap Supervisor mode (privileged instructions) Illegal instruction trap Coprocessor emulation trap Burst mode memory access Multiprocessor support, with many bus configuration modes Support for multiple external coprocessors through an accelerated communication interface Multiple I/O pages, which also allows for internal I/O devices without restricting the address range of the I/O ports like on eZ80, or conflicting with existing motherboard devices, like the Z180. Stack overflow warning In the early 1990s, a small number of single-board computers based on the Zilog Z280 were designed and produced by Tilmann Reh, but the CPU was never used in any commercially produced computer. In 2016, Lamar Owens contacted Tilmann Reh and obtained permission to have a small new run of the CPU280 system PCBs created, getting ten boards made and distributed to several beta builders. Wayne Warthen developed a build setup to rebuild the EPROM images and floppy disk images, and set up a page at GitHub for distribution and development. In spring 2018, another ten boards were made.
A kernel is a computer program at the core of a computer's operating system that always has complete control over everything in the system. The kernel is also responsible for preventing and mitigating conflicts between different processes. It is the portion of the operating system that is always resident in memory and facilitates interactions between hardware and software components. A full kernel controls all hardware resources (e.g. I/O, memory, cryptography) via device drivers, arbitrates conflicts between processes concerning such resources, and optimizes the use of common resources, such as CPU, cache, file systems, and network sockets. On most systems, the kernel is one of the first programs loaded on startup (after the bootloader). It handles the rest of startup as well as memory, peripherals, and input/output (I/O) requests from software, translating them into data-processing instructions for the central processing unit. The critical code of the kernel is usually loaded into a separate area of memory, which is protected from access by application software or other less critical parts of the operating system. The kernel performs its tasks, such as scheduling processes, managing hardware devices such as the hard disk, and handling interrupts, in this protected kernel space. In contrast, application programs such as browsers, word processors, or audio or video players use a separate area of memory, user space. This prevents user data and kernel data from interfering with each other and causing instability and slowness, as well as preventing malfunctioning applications from affecting other applications or crashing the entire operating system. Even in systems where the kernel is included in application address spaces, memory protection is used to prevent unauthorized applications from modifying the kernel. The kernel's interface is a low-level abstraction layer. When a process requests a service from the kernel, it must invoke a system call, usually through a wrapper function. There are different kernel architecture designs. Monolithic kernels run entirely in a single address space with the CPU executing in supervisor mode, mainly for speed. Microkernels run most but not all of their services in user space, like user processes do, mainly for resilience and modularity. MINIX 3 is a notable example of microkernel design. Some kernels, such as the Linux kernel, are both monolithic and modular, since they can insert and remove loadable kernel modules at runtime. This central component of a computer system is responsible for executing programs. The kernel takes responsibility for deciding at any time which of the many running programs should be allocated to the processor or processors.
The maximum random access memory (RAM) installed in any computer system is limited by hardware, software and economic factors. The hardware may have a limited number of address bus bits, limited by the processor package or design of the system. Some of the address space may be shared between RAM, peripherals, and read-only memory. In the case of a microcontroller with no external RAM, the size of the RAM array is limited by the size of the integrated circuit die. In a packaged system, only enough RAM may be provided for the system's required functions, with no provision for addition of memory after manufacture. Software limitations to usable physical RAM may be present. An operating system may only be designed to allocate a certain amount of memory, with upper address bits reserved to indicate designations such as I/O or supervisor mode or other security information. Or the operating system may rely on internal data structures with fixed limits for addressable memory. For mass-market personal computers, there may be no financial advantage to a manufacturer in providing more memory sockets, address lines, or other hardware than necessary to run mass-market software. When memory devices were relatively expensive compared with the processor, often the RAM delivered with the system was much less than the address capacity of the hardware, because of cost. Sometimes RAM limits can be overcome using special techniques. Bank switching allows blocks of RAM memory to be switched into the processor's address space when required, under program control. Operating systems routinely manage running programs using virtual memory, where individual program operate as if they have access to a large memory space that is being simulated by swapping memory areas with disk storage.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Madam C.J. Walker
