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Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers.
There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (Advanced Bit Manipulation, which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (Trailing Bit Manipulation, an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors).[1]
AMD was the first to introduce the instructions that now form Intel's BMI1 as part of its ABM (Advanced Bit Manipulation) instruction set, then later added support for Intel's new BMI2 instructions. AMD today advertises the availability of these features via Intel's BMI1 and BMI2 cpuflags and instructs programmers to target them accordingly.[2]
While Intel considers POPCNT as part of SSE4.2 and LZCNT as part of BMI1, both Intel and AMD advertise the presence of these two instructions individually. POPCNT has a separate CPUID flag of the same name, and Intel and AMD use AMD's ABM flag to indicate LZCNT support (since LZCNT combined with BMI1 and BMI2 completes the expanded ABM instruction set).[2][3]
| Encoding | Instruction | Description[4] |
|---|---|---|
F3 0F B8 /r
|
POPCNT
|
Population count |
F3 0F BD /r
|
LZCNT
|
Leading zeros count |
LZCNT is related to the Bit Scan Reverse (BSR) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). Also, it produces a defined result (the source operand size in bits) if the source operand is zero. For a non-zero argument, sum of LZCNT and BSR results is argument bit width minus 1 (for example, if 32-bit argument is 0x000f0000, LZCNT gives 12, and BSR gives 19).
The encoding of LZCNT is such that if ABM is not supported, then the BSR instruction is executed instead.[4]: 227
The instructions below are those enabled by the BMI bit in CPUID. Intel officially considers LZCNT as part of BMI, but advertises LZCNT support using the ABM CPUID feature flag.[3] BMI1 is available in AMD's Jaguar,[5] Piledriver[6] and newer processors, and in Intel's Haswell[7] and newer processors.
| Encoding | Instruction | Description[3] | Equivalent C expression[8][9][10] |
|---|---|---|---|
VEX.LZ.0F38 F2 /r
|
ANDN
|
Logical and not | ~x & y
|
VEX.LZ.0F38 F7 /r
|
BEXTR
|
Bit field extract (with register) | (src >> start) & ((1 << len) - 1)
|
VEX.LZ.0F38 F3 /3
|
BLSI
|
Extract lowest set isolated bit | x & -x
|
VEX.LZ.0F38 F3 /2
|
BLSMSK
|
Get mask up to lowest set bit | x ^ (x - 1)
|
VEX.LZ.0F38 F3 /1
|
BLSR
|
Reset lowest set bit | x & (x - 1)
|
F3 0F BC /r
|
TZCNT
|
Count the number of trailing zero bits | 31 + (!x)
- (((x & -x) & 0x0000FFFF) ? 16 : 0)
- (((x & -x) & 0x00FF00FF) ? 8 : 0)
- (((x & -x) & 0x0F0F0F0F) ? 4 : 0)
- (((x & -x) & 0x33333333) ? 2 : 0)
- (((x & -x) & 0x55555555) ? 1 : 0)
|
TZCNT is almost identical to the Bit Scan Forward (BSF) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). For a non-zero argument, the result of TZCNT and BSF is equal.
As with LZCNT, the encoding of TZCNT is such that if BMI1 is not supported, then the BSF instruction is executed instead.[4]: 352
Intel introduced BMI2 together with BMI1 in its line of Haswell processors. Only AMD has produced processors supporting BMI1 without BMI2; BMI2 is supported by AMDs Excavator architecture and newer.[11]
| Encoding | Instruction | Description |
|---|---|---|
VEX.LZ.0F38 F5 /r
|
BZHI
|
Zero high bits starting with specified bit position [src & (1 << inx)-1]; |
VEX.LZ.F2.0F38 F6 /r
|
MULX
|
Unsigned multiply without affecting flags, and arbitrary destination registers |
VEX.LZ.F2.0F38 F5 /r
|
PDEP
|
Parallel bits deposit |
VEX.LZ.F3.0F38 F5 /r
|
PEXT
|
Parallel bits extract |
VEX.LZ.F2.0F3A F0 /r ib
|
RORX
|
Rotate right logical without affecting flags |
VEX.LZ.F3.0F38 F7 /r
|
SARX
|
Shift arithmetic right without affecting flags |
VEX.LZ.F2.0F38 F7 /r
|
SHRX
|
Shift logical right without affecting flags |
VEX.LZ.66.0F38 F7 /r
|
SHLX
|
Shift logical left without affecting flags |
The PDEP and PEXT instructions are new generalized bit-level compress and expand instructions. They take two inputs; one is a source, and the other is a selector. The selector is a bitmap selecting the bits that are to be packed or unpacked. PEXT copies selected bits from the source to contiguous low-order bits of the destination; higher-order destination bits are cleared. PDEP does the opposite for the selected bits: contiguous low-order bits are copied to selected bits of the destination; other destination bits are cleared. This can be used to extract any bitfield of the input, and even do a lot of bit-level shuffling that previously would have been expensive. While what these instructions do is similar to bit level gather-scatter SIMD instructions, PDEP and PEXT instructions (like the rest of the BMI instruction sets) operate on general-purpose registers.[12]
The instructions are available in 32-bit and 64-bit versions. An example using arbitrary source and selector in 32-bit mode is:
| Instruction | Selector mask | Source | Destination |
|---|---|---|---|
PEXT |
0xff00fff0 |
0x12345678 |
0x00012567
|
PDEP |
0xff00fff0 |
0x00012567 |
0x12005670
|
AMD processors before Zen 3[13] that implement PDEP and PEXT do so in microcode, with a latency of 18 cycles[14] rather than (Zen 3) 3 cycles.[15] As a result it is often faster to use other instructions on these processors.[16]
TBM consists of instructions complementary to the instruction set started by BMI1; their complementary nature means they do not necessarily need to be used directly but can be generated by an optimizing compiler when supported. AMD introduced TBM together with BMI1 in its Piledriver[6] line of processors; later AMD Jaguar and Zen-based processors do not support TBM.[5] No Intel processors (through Nova Lake) support TBM.
| Encoding | Instruction | Description[4] | Equivalent C expression[17][9] |
|---|---|---|---|
XOP.LZ.0A 10 /r id
|
BEXTR
|
Bit field extract (with immediate) | (src >> start) & ((1 << len) - 1)
|
XOP.LZ.09 01 /1
|
BLCFILL
|
Fill from lowest clear bit | x & (x + 1)
|
XOP.LZ.09 02 /6
|
BLCI
|
Isolate lowest clear bit | x | ~(x + 1)
|
XOP.LZ.09 01 /5
|
BLCIC
|
Isolate lowest clear bit and complement | ~x & (x + 1)
|
XOP.LZ.09 02 /1
|
BLCMSK
|
Mask from lowest clear bit | x ^ (x + 1)
|
XOP.LZ.09 01 /3
|
BLCS
|
Set lowest clear bit | x | (x + 1)
|
XOP.LZ.09 01 /2
|
BLSFILL
|
Fill from lowest set bit | x | (x - 1)
|
XOP.LZ.09 01 /6
|
BLSIC
|
Isolate lowest set bit and complement | ~x | (x - 1)
|
XOP.LZ.09 01 /7
|
T1MSKC
|
Inverse mask from trailing ones | ~x | (x + 1)
|
XOP.LZ.09 01 /4
|
TZMSK
|
Mask from trailing zeros | ~x & (x - 1)
|
Note that instruction extension support means the processor is capable of executing the supported instructions for software compatibility purposes. The processor might not perform well doing so. For example, Excavator through Zen 2 processors implement PEXT and PDEP instructions using microcode resulting in the instructions executing significantly slower than the same behaviour recreated using other instructions.[20] (A software method called "zp7" is, in fact, faster on these machines.)[21] For optimum performance it is recommended that compiler developers choose to use individual instructions in the extensions based on architecture specific performance profiles rather than on extension availability.
Source: Wikipedia. Article content is retrieved live through the MediaWiki API.
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers. There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (Advanced Bit Manipulation, which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (Trailing Bit Manipulation, an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors).
In a central processing unit (CPU), a status register, flag register, or condition code register (CCR) is a register that stores flags (bits) indicating the processor state and results of operations. Examples of such registers include the FLAGS register in x86 CPUs, the program status word (PSW) register in IBM's System/360 through z/Architecture, the application program status register (APSR) in 32-bit ARM architectures, and the NCSV system register in AArch64. The status register contains information about the state of the processor. Individual bits are implicitly or explicitly read or written by the machine code instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction. Typically, some of the flags in a status register are modified as a result of arithmetic and bit manipulation operations performed by the arithmetic logic unit (ALU). For example, a Z status bit may be set if the result of an operation is zero or cleared if it is nonzero. A string instruction may modify a status flag to indicate whether it terminated due to finding a match or reaching the end of the string. Some flags are used later by conditional instructions to control program execution. Some instruction set architectures (ISAs) do not use a dedicated flag register, such as the MIPS and Alpha; others do not implicitly set or read flags. Such machines either do not pass implicit status information between instructions or pass it in a general purpose register. A status register may have additional fields such as privilege flags, interrupt enable bits, and other types of information. During an interrupt, the status of the currently executing thread can be preserved by storing the current value of the status register (along with the program counter and other active registers) to the machine stack or other memory.
The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011. However AMD removed support for XOP from Zen (microarchitecture) onward. The XOP instruction set contains several different types of vector instructions since it was originally intended as a major upgrade to SSE. Most of the instructions are integer instructions, but it also contains floating point permutation and floating point fraction extraction instructions. See the index for a list of instruction types.
The FMA instruction set is an extension to the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations on 128-bit and 256-bit operands. These operations were extended to 512-bit operands by the AVX-512 extension introduced by Intel and later supported by AMD. There are two incompatible variants of the FMA instruction set. They have the same operations but differ in the number of operands: FMA4 is the four-operand variant (three source operands and a destination register). AMD added FMA4 with the Bulldozer (2011) architecture. Zen 1 (2017) processors still execute FMA4 instructions but do not report them as supported through CPUID, and Zen 2 (2019) removed them. Intel originally specified FMA4 in 2008, but changed its design to three operands later that year. FMA3 is the three-operand variant (three source operands, one of which is also the destination). AMD added FMA3 with the Piledriver (2012) architecture, for compatibility with Intel's planned Haswell processors. Intel added FMA3, alongside AVX2, with Haswell (2013) processors. Earlier processors, including AMD's Bulldozer and Intel's Sandy Bridge and Ivy Bridge, do not support it. AVX-512 adds 512-bit forms of the FMA3 instructions.
Before the 1921 destruction of Tulsa’s Greenwood District, Black residents had created a remarkable center of business and community life. The district included stores, professional offices, entertainment venues and homes owned by Black citizens. Understanding Greenwood means learning what was built—not only what was burned.
MORE →Madam C.J. Walker
